The invention relates to the design and manufacture of integrated circuits, and more particularly, to systems and methods for performing parallel processing of electronic design automation (EDA) tools.
The electronic design process for an integrated circuit (IC) involves describing the behavioral, architectural, functional, and structural attributes of an IC or electronic system. Design teams often begin with very abstract behavioral models of the intended product and end with a physical description of the numerous structures, devices, and interconnections on an IC chip. Semiconductor foundries use the physical description to create the masks and test programs needed to manufacture the ICs. EDA tools are extensively used by designers throughout the process of designing and verifying electronic designs.
A Physical Verification (PV) tool is a common example of a EDA tool that is used by electronics designers. PV is one of the final steps that is performed before releasing an IC design to manufacturing. Physical verification ensures that the design abides by all of the detailed rules and parameters that the foundry specifies for its manufacturing process. Violating a single foundry rule can result in a silicon product that does not work for its intended purpose. Therefore, it is critical that thorough PV processing is performed before finalizing an IC design. Physical Verification tools may be used frequently and at many stages of the IC design process. As noted above, PV tools may be used during design and at tape-out to ensure compliance with physical and electrical constraints imposed by the manufacturing process. In addition, PV tools may also be used after tape-out to verify and ensure manufacturability of the design and its constituent elements.
PV tools read and manipulate a design database which stores information about device geometries and connectivity. Because compliance with design rules generally constitutes the gating factor between one stage of the design and the next, PV tools are typically executed multiple times during the evolution of the design and contribute significantly to the project's critical path. Therefore, reducing PV tool execution time makes a major contribution to the reduction of overall design cycle times.
As the quantity of data in modern IC designs become larger and larger over time, the execution time required to process EDA tools upon these IC designs also becomes greater. For example, the goal of reducing PV tool execution time is in sharp tension with many modern IC designs being produced by electronics companies that are constantly increasing in complexity and number of transistors. The more transistors and other structures on an IC design, the greater amounts of time that is normally needed to perform PV processing. This problem is exasperated for all EDA tools by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, as well resulting in more complex physical and lithographic effects during manufacture.
To improve the processing of EDA tools, the present invention provide an improved method and system for processing the tasks performed by an EDA tool in parallel. In some embodiment of the invention, the IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Methods are described for some embodiments for sampling one or more windows to provide dynamic performance estimation.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.